This invention relates to the testing of memory array devices, more particularly to an apparatus for performing such tests.
It is often necessary to test an integrated circuit device. e.g., immediately after manufacturing such a device or while performing repairs, and this is typically done by providing a common input to both the device under test (DUT) and to a standard, or reference, device. The outputs of the two devices are then compared, with any disagreement indicating a failure. In the testing of memory array devices, data is supplied to the reference and test memories along with common address signaling designating storage locations. The memories are then read out, again using common address signaling, and the outputs are examined for any disagreement.
If the memory testing system is designed to test only a single memory, a standard memory of the same configuration as the test memory can be employed with an address generator compatible with both memories. However, in the case of an independent testing unit which is intended to test a wide variety of products, a memory under test will not always be of the same configuration as the standard memory. For example, memories are generally some X size by some Y size, and an 8 Kbit memory may be configured with 32 X lines and 256 Y lines requiring five X address line inputs and eight Y address line inputs. A different memory may be a 64 Kbit memory requiring twelve X address lines and four Y address lines. To ensure that the memory tester is capable of addressing any memory configuration, it would be preferable to utilize an address generator having a 24-bit address output capability, i.e. a 12-bit X address and a 12-bit Y address.
If a standard memory is employed which is capable of accepting either a 12-bit X address or a 12-bit Y address, a memory capacity of 16 megabits will be required. This would be extremely wasteful and expensive, since the largest memory to be tested may be 64 Kbits. This problem is further compounded if a testing device is designed to test other devices which may require as many as 16 bits of either an X input or a Y input, thus necessitating an address generator having a 32-bit output. A standard memory having the same capacity as the address generator would have approximately 64 megabits of memory capacity.
By way of Example, FIG. 1 illustrates a memory testing configuration in which random data is supplied from data generator 10 and, in response to a write signal on line 12, the data is stored in both a standard memory 14 and test memory 16 at addresses determined by random address generator 18. Subsequently, in response to a read pulse on line 12, the data is then read out of the memories 14 and 16 in response to random addresses from address generator 18, and the outputs are compared in error logic circuitry 20. The test memory 16 may have any one of a variety of configurations but, for the purposes of this explanation, it will be assumed to have a maximum memory capacity 64 Kbits. Accordingly, the memory 16 may require an address signal of up to 16 bits divided between the X and Y dimensions of the memory in any number of ways. For example, the memory may require a 4-bit X address and a 12-bit Y address, or it could conceivably require merely a 16-bit X address input with no address in the Y direction. In order to provide the capability of addressing any memory configuration of up to 64 Kbits, the address generator 18 must be capable of providing up to 16 bits of address in either the X or Y directions, thus requiring a 32 bit address generation capacity. If the address to the test memory, for example, must be a 4X by 12Y address, the first twelve X address bits and the first four Y address bits will simply be ignored.
A problem, however, arises with the standard memory 14. As mentioned above, a 64 megabit memory would be required to accommodate all of the 32-bit output of the address generator 18. This need for excessive memory capacity could be eliminated by utilizing a standard memory having the same configuration as the test memory and by also using an address generator providing the proper number of address outputs, but the flexibility of the testing apparatus would be lost in that the apparatus would be capable of testing only a single memory of fixed size and configuration.